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 .D(shift_value[5]),
 .Q(shift_result[5]),
 .R(sel_shift),
 .C(clk));

 // synthesis translate_off 
 defparam shift_mux_lut_6.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 shift_mux_lut_6 ( 
 .I0(instruction[3]),
 .I1(sx[5]),
 .I2(sx[7]),
 .O(shift_value[6]))/* synthesis xc_props = "INIT=E4"*/;

 FDR shift_flop_6 ( 
 .D(shift_value[6]),
 .Q(shift_result[6]),
 .R(sel_shift),
 .C(clk));

 // synthesis translate_off 
 defparam shift_mux_lut_7.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 shift_mux_lut_7 ( 
 .I0(instruction[3]),
 .I1(sx[6]),
 .I2(shift_in),
 .O(shift_value[7]) )/* synthesis xc_props = "INIT=E4"*/;
   
 FDR shift_flop_7 ( 
 .D(shift_value[7]),
 .Q(shift_result[7]),
 .R(sel_shift),
 .C(clk));

//
////////////////////////////////////////////////////////////////////////////////////
//
// Arithmetic operations
//
// Definition of ADD, ADDCY, SUB and SUBCY functions which also provides COMPARE.
// Includes pipeline stage used to form ALU multiplexer including decode.
//
////////////////////////////////////////////////////////////////////////////////////
//
 // synthesis translate_off 
 defparam sel_arith_lut.INIT = 8'h1F;
 // synthesis translate_on 
 LUT3 sel_arith_lut ( 
 .I0(instruction[14]),
 .I1(instruction[15]),
 .I2(instruction[16]),
 .O(sel_arith))/* synthesis xc_props = "INIT=1F"*/; 
 
 //arith_loop 

 // synthesis translate_off 
 defparam arith_carry_in_lut.INIT = 8'h6C;
 // synthesis translate_on 
 LUT3 arith_carry_in_lut ( 
 .I0(instruction[13]),
 .I1(instruction[14]),
 .I2(carry_flag),
 .O(sel_arith_carry_in ))/* synthesis xc_props = "INIT=6C"*/;

 MUXCY arith_carry_in_muxcy ( 
 .DI(1'b0),
 .CI(1'b1),
 .S(sel_arith_carry_in),
 .O(arith_carry_in));

 MUXCY arith_muxcy_0 ( 
 .DI(sx[0]),
 .CI(arith_carry_in),
 .S(half_arith[0]),
 .O(arith_internal_carry[0]));
 
 XORCY arith_xor_0 ( 
 .LI(half_arith[0]),
 .CI(arith_carry_in),
 .O(arith_value[0]));

 // synthesis translate_off 
 defparam arith_lut_0.INIT = 8'h96;
 // synthesis translate_on 
 LUT3 arith_lut_0 ( 
 .I0(sx[0]),
 .I1(second_operand[0]),
 .I2(instruction[14]),
 .O(half_arith[0]))/* synthesis xc_props = "INIT=96"*/;

 FDR arith_flop_0 ( 
 .D(arith_value[0]),
 .Q(arith_result[0]),
 .R(sel_arith),
 .C(clk));
 
 MUXCY arith_muxcy_1 ( 
 .DI(sx[1]),
 .CI(arith_internal_carry[0]),
 .S(half_arith[1]),
 .O(arith_internal_carry[1]));

 XORCY arith_xor_1 ( 
 .LI(half_arith[1]),
 .CI(arith_internal_carry[0]),
 .O(arith_value[1]));

 // synthesis translate_off 
 defparam arith_lut_1.INIT = 8'h96;
 // synthesis translate_on 
 LUT3 arith_lut_1 ( 
 .I0(sx[1]),
 .I1(second_operand[1]),
 .I2(instruction[14]),
 .O(half_arith[1]))/* synthesis xc_props = "INIT=96"*/;

 FDR arith_flop_1 ( 
 .D(arith_value[1]),
 .Q(arith_result[1]),
 .R(sel_arith),
 .C(clk));
 
 MUXCY arith_muxcy_2 ( 
 .DI(sx[2]),
 .CI(arith_internal_carry[1]),
 .S(half_arith[2]),
 .O(arith_internal_carry[2]));

 XORCY arith_xor_2 ( 
 .LI(half_arith[2]),
 .CI(arith_internal_carry[1]),
 .O(arith_value[2]));

 // synthesis translate_off 
 defparam arith_lut_2.INIT = 8'h96;
 // synthesis translate_on 
 LUT3 arith_lut_2 ( 
 .I0(sx[2]),
 .I1(second_operand[2]),
 .I2(instruction[14]),
 .O(half_arith[2]))/* synthesis xc_props = "INIT=96"*/;

 FDR arith_flop_2 ( 
 .D(arith_value[2]),
 .Q(arith_result[2]),
 .R(sel_arith),
 .C(clk));
  
 MUXCY arith_muxcy_3 ( 
 .DI(sx[3]),
 .CI(arith_internal_carry[2]),
 .S(half_arith[3]),
 .O(arith_internal_carry[3]));

 XORCY arith_xor_3 ( 
 .LI(half_arith[3]),
 .CI(arith_internal_carry[2]),
 .O(arith_value[3]));

 // synthesis translate_off 
 defparam arith_lut_3.INIT = 8'h96;
 // synthesis translate_on 
 LUT3 arith_lut_3 ( 
 .I0(sx[3]),
 .I1(second_operand[3]),
 .I2(instruction[14]),
 .O(half_arith[3]))/* synthesis xc_props = "INIT=96"*/;

 FDR arith_flop_3 ( 
 .D(arith_value[3]),
 .Q(arith_result[3]),
 .R(sel_arith),
 .C(clk));
 
 MUXCY arith_muxcy_4 ( 
 .DI(sx[4]),
 .CI(arith_internal_carry[3]),
 .S(half_arith[4]),
 .O(arith_internal_carry[4]));

 XORCY arith_xor_4 ( 
 .LI(half_arith[4]),
 .CI(arith_internal_carry[3]),
 .O(arith_value[4]));

 // synthesis translate_off 
 defparam arith_lut_4.INIT = 8'h96;
 // synthesis translate_on 
 LUT3 arith_lut_4 ( 
 .I0(sx[4]),
 .I1(second_operand[4]),
 .I2(instruction[14]),
 .O(half_arith[4]))/* synthesis xc_props = "INIT=96"*/;

 FDR arith_flop_4 ( 
 .D(arith_value[4]),
 .Q(arith_result[4]),
 .R(sel_arith),
 .C(clk));
  
 MUXCY arith_muxcy_5 ( 
 .DI(sx[5]),
 .CI(arith_internal_carry[4]),
 .S(half_arith[5]),
 .O(arith_internal_carry[5]));

 XORCY arith_xor_5 ( 
 .LI(half_arith[5]),
 .CI(arith_internal_carry[4]),
 .O(arith_value[5]));    

 // synthesis translate_off 
 defparam arith_lut_5.INIT = 8'h96;
 // synthesis translate_on 
 LUT3 arith_lut_5 ( 
 .I0(sx[5]),
 .I1(second_operand[5]),
 .I2(instruction[14]),
 .O(half_arith[5]))/* synthesis xc_props = "INIT=96"*/;

 FDR arith_flop_5 ( 
 .D(arith_value[5]),
 .Q(arith_result[5]),
 .R(sel_arith),
 .C(clk));
 
 MUXCY arith_muxcy_6 ( 
 .DI(sx[6]),
 .CI(arith_internal_carry[5]),
 .S(half_arith[6]),
 .O(arith_internal_carry[6]));

 XORCY arith_xor_6 ( 
 .LI(half_arith[6]),
 .CI(arith_internal_carry[5]),
 .O(arith_value[6]));

 // synthesis translate_off 
 defparam arith_lut_6.INIT = 8'h96;
 // synthesis translate_on 
 LUT3 arith_lut_6 ( 
 .I0(sx[6]),
 .I1(second_operand[6]),
 .I2(instruction[14]),
 .O(half_arith[6]))/* synthesis xc_props = "INIT=96"*/;

 FDR arith_flop_6 ( 
 .D(arith_value[6]),
 .Q(arith_result[6]),
 .R(sel_arith),
 .C(clk));
 
 MUXCY arith_muxcy_7 ( 
 .DI(sx[7]),
 .CI(arith_internal_carry[6]),
 .S(half_arith[7]),
 .O(arith_internal_carry[7]));

 XORCY arith_xor_7 ( 
 .LI(half_arith[7]),
 .CI(arith_internal_carry[6]),
 .O(arith_value[7]));

 // synthesis translate_off 
 defparam arith_carry_out_lut.INIT = 2'h2;
 // synthesis translate_on 
 LUT1 arith_carry_out_lut ( 
 .I0(instruction[14]),
 .O(invert_arith_carry ))/* synthesis xc_props = "INIT=2"*/;
 
  XORCY arith_carry_out_xor ( 
 .LI(invert_arith_carry),
 .CI(arith_internal_carry[7]),
 .O(arith_carry_out));

 // synthesis translate_off 
 defparam arith_lut_7.INIT = 8'h96;
 // synthesis translate_on 
 LUT3 arith_lut_7 ( 
 .I0(sx[7]),
 .I1(second_operand[7]),
 .I2(instruction[14]),
 .O(half_arith[7]))/* synthesis xc_props = "INIT=96"*/;

 FDR arith_flop_7 ( 
 .D(arith_value[7]),
 .Q(arith_result[7]),
 .R(sel_arith),
 .C(clk));
 
 FDR arith_carry_flop ( 
 .D(arith_carry_out),
 .Q(arith_carry),
 .R(sel_arith),
 .C(clk));
//
////////////////////////////////////////////////////////////////////////////////////
//
// ALU multiplexer
//
////////////////////////////////////////////////////////////////////////////////////
//
 // synthesis translate_off 
 defparam input_fetch_type_lut.INIT = 16'h0002;
 // synthesis translate_on 
 LUT4 input_fetch_type_lut ( 
 .I0(instruction[14]),
 .I1(instruction[15]),
 .I2(instruction[16]),
 .I3(instruction[17]),
 .O(input_fetch_type ))/* synthesis xc_props = "INIT=0002"*/;

 FD sel_group_flop ( 
 .D(input_fetch_type),
 .Q(sel_group),
 .C(clk));
 
 //alu_mux_loop 

 // synthesis translate_off 
 defparam or_lut_0.INIT = 8'hFE;
 // synthesis translate_on 
 LUT3 or_lut_0 ( 
 .I0(logical_result[0]),
 .I1(arith_result[0]),
 .I2(shift_result[0]),
 .O(alu_group[0]))/* synthesis xc_props = "INIT=FE"*/;

 // synthesis translate_off 
 defparam mux_lut_0.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 mux_lut_0 ( 
 .I0(instruction[13]),
 .I1(in_port[0]),
 .I2(store_data[0]),
 .O(input_group[0]))/* synthesis xc_props = "INIT=E4"*/;

 MUXF5 shift_in_muxf5_0 ( 
 .I1(input_group[0]),
 .I0(alu_group[0]),
 .S(sel_group),
 .O(alu_result[0]) ); 

 // synthesis translate_off 
 defparam or_lut_1.INIT = 8'hFE;
 // synthesis translate_on 
 LUT3 or_lut_1 ( 
 .I0(logical_result[1]),
 .I1(arith_result[1]),
 .I2(shift_result[1]),
 .O(alu_group[1]))/* synthesis xc_props = "INIT=FE"*/;

 // synthesis translate_off 
 defparam mux_lut_1.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 mux_lut_1 ( 
 .I0(instruction[13]),
 .I1(in_port[1]),
 .I2(store_data[1]),
 .O(input_group[1]))/* synthesis xc_props = "INIT=E4"*/;

 MUXF5 shift_in_muxf5_1 ( 
 .I1(input_group[1]),
 .I0(alu_group[1]),
 .S(sel_group),
 .O(alu_result[1]) ); 

 // synthesis translate_off 
 defparam or_lut_2.INIT = 8'hFE;
 // synthesis translate_on 
 LUT3 or_lut_2 ( 
 .I0(logical_result[2]),
 .I1(arith_result[2]),
 .I2(shift_result[2]),
 .O(alu_group[2]))/* synthesis xc_props = "INIT=FE"*/;

 // synthesis translate_off 
 defparam mux_lut_2.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 mux_lut_2 ( 
 .I0(instruction[13]),
 .I1(in_port[2]),
 .I2(store_data[2]),
 .O(input_group[2]))/* synthesis xc_props = "INIT=E4"*/;

 MUXF5 shift_in_muxf5_2 ( 
 .I1(input_group[2]),
 .I0(alu_group[2]),
 .S(sel_group),
 .O(alu_result[2]) ); 

 // synthesis translate_off 
 defparam or_lut_3.INIT = 8'hFE;
 // synthesis translate_on 
 LUT3 or_lut_3 ( 
 .I0(logical_result[3]),
 .I1(arith_result[3]),
 .I2(shift_result[3]),
 .O(alu_group[3]))/* synthesis xc_props = "INIT=FE"*/;

 // synthesis translate_off 
 defparam mux_lut_3.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 mux_lut_3 ( 
 .I0(instruction[13]),
 .I1(in_port[3]),
 .I2(store_data[3]),
 .O(input_group[3]))/* synthesis xc_props = "INIT=E4"*/;

 MUXF5 shift_in_muxf5_3 ( 
 .I1(input_group[3]),
 .I0(alu_group[3]),
 .S(sel_group),
 .O(alu_result[3]) ); 
  
 // synthesis translate_off 
 defparam or_lut_4.INIT = 8'hFE;
 // synthesis translate_on 
 LUT3 or_lut_4 ( 
 .I0(logical_result[4]),
 .I1(arith_result[4]),
 .I2(shift_result[4]),
 .O(alu_group[4]))/* synthesis xc_props = "INIT=FE"*/;

 // synthesis translate_off 
 defparam mux_lut_4.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 mux_lut_4 ( 
 .I0(instruction[13]),
 .I1(in_port[4]),
 .I2(store_data[4]),
 .O(input_group[4]))/* synthesis xc_props = "INIT=E4"*/;

 MUXF5 shift_in_muxf5_4 ( 
 .I1(input_group[4]),
 .I0(alu_group[4]),
 .S(sel_group),
 .O(alu_result[4]) ); 
 
  // synthesis translate_off 
 defparam or_lut_5.INIT = 8'hFE;
 // synthesis translate_on 
 LUT3 or_lut_5 ( 
 .I0(logical_result[5]),
 .I1(arith_result[5]),
 .I2(shift_result[5]),
 .O(alu_group[5]))/* synthesis xc_props = "INIT=FE"*/;

 // synthesis translate_off 
 defparam mux_lut_5.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 mux_lut_5 ( 
 .I0(instruction[13]),
 .I1(in_port[5]),
 .I2(store_data[5]),
 .O(input_group[5]))/* synthesis xc_props = "INIT=E4"*/;

 MUXF5 shift_in_muxf5_5 ( 
 .I1(input_group[5]),
 .I0(alu_group[5]),
 .S(sel_group),
 .O(alu_result[5]) ); 

 // synthesis translate_off 
 defparam or_lut_6.INIT = 8'hFE;
 // synthesis translate_on 
 LUT3 or_lut_6 ( 
 .I0(logical_result[6]),
 .I1(arith_result[6]),
 .I2(shift_result[6]),
 .O(alu_group[6]))/* synthesis xc_props = "INIT=FE"*/;

 // synthesis translate_off 
 defparam mux_lut_6.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 mux_lut_6 ( 
 .I0(instruction[13]),
 .I1(in_port[6]),
 .I2(store_data[6]),
 .O(input_group[6]))/* synthesis xc_props = "INIT=E4"*/;

 MUXF5 shift_in_muxf5_6 ( 
 .I1(input_group[6]),
 .I0(alu_group[6]),
 .S(sel_group),
 .O(alu_result[6]) ); 
  
 // synthesis translate_off 
 defparam or_lut_7.INIT = 8'hFE;
 // synthesis translate_on 
 LUT3 or_lut_7 ( 
 .I0(logical_result[7]),
 .I1(arith_result[7]),
 .I2(shift_result[7]),
 .O(alu_group[7]))/* synthesis xc_props = "INIT=FE"*/;

 // synthesis translate_off 
 defparam mux_lut_7.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 mux_lut_7 ( 
 .I0(instruction[13]),
 .I1(in_port[7]),
 .I2(store_data[7]),
 .O(input_group[7]))/* synthesis xc_props = "INIT=E4"*/;

 MUXF5 shift_in_muxf5_7 ( 
 .I1(input_group[7]),
 .I0(alu_group[7]),
 .S(sel_group),
 .O(alu_result[7]) );   
 //
////////////////////////////////////////////////////////////////////////////////////
//
// Read and Write Strobes
//
////////////////////////////////////////////////////////////////////////////////////
//
 // synthesis translate_off 
 defparam io_decode_lut.INIT = 16'h0010;
 // synthesis translate_on 
 LUT4 io_decode_lut ( 
 .I0(active_interrupt),
 .I1(instruction[13]),
 .I2(instruction[14]),
 .I3(instruction[16]),
 .O(io_initial_decode ))/* synthesis xc_props = "INIT=0010"*/;

 // synthesis translate_off 
 defparam write_active_lut.INIT = 16'h4000;
 // synthesis translate_on 
 LUT4 write_active_lut ( 
 .I0(t_state),
 .I1(instruction[15]),
 .I2(instruction[17]),
 .I3(io_initial_decode),
 .O(write_active ))/* synthesis xc_props = "INIT=4000"*/;

 FDR write_strobe_flop ( 
 .D(write_active),
 .Q(write_strobe),
 .R(internal_reset),
 .C(clk));

 // synthesis translate_off 
 defparam read_active_lut.INIT = 16'h0100;
 // synthesis translate_on 
 LUT4 read_active_lut ( 
 .I0(t_state),
 .I1(instruction[15]),
 .I2(instruction[17]),
 .I3(io_initial_decode),
 .O(read_active ))/* synthesis xc_props = "INIT=0100"*/;

 FDR read_strobe_flop ( 
 .D(read_active),
 .Q(read_strobe),
 .R(internal_reset),
 .C(clk));
//
////////////////////////////////////////////////////////////////////////////////////
//
// Program CALL/RETURN stack
//
// Provided the counter and memory for a 32 deep stack supporting nested 
// subroutine calls to a depth of 31 levels.
//
////////////////////////////////////////////////////////////////////////////////////
//
 // Stack memory is 32 locations of 10-bit single port.
 
 INV stack_ram_inv ( // Inverter should be implemented in the WE to RAM
 .I(t_state),
 .O(stack_write_enable)); 
 
 //stack_ram_loop 
 
 // synthesis translate_off 
 defparam stack_bit_0.INIT = 32'h00000000;
 // synthesis translate_on 
 RAM32X1S stack_bit_0 ( 
 .D(pc[0]),
 .WE(stack_write_enable),
 .WCLK(clk),
 .A0(stack_address[0]),
 .A1(stack_address[1]),
 .A2(stack_address[2]),
 .A3(stack_address[3]),
 .A4(stack_address[4]),
 .O(stack_ram_data[0]))/* synthesis xc_props = "INIT=00000000"*/;

 FD stack_flop_0 ( 
 .D(stack_ram_data[0]),
 .Q(stack_pop_data[0]),
 .C(clk));

 // synthesis translate_off 
 defparam stack_bit_1.INIT = 32'h00000000;
 // synthesis translate_on 
 RAM32X1S stack_bit_1 ( 
 .D(pc[1]),
 .WE(stack_write_enable),
 .WCLK(clk),
 .A0(stack_address[0]),
 .A1(stack_address[1]),
 .A2(stack_address[2]),
 .A3(stack_address[3]),
 .A4(stack_address[4]),
 .O(stack_ram_data[1]))/* synthesis xc_props = "INIT=00000000"*/;

 FD stack_flop_1 ( 
 .D(stack_ram_data[1]),
 .Q(stack_pop_data[1]),
 .C(clk));

 // synthesis translate_off 
 defparam stack_bit_2.INIT = 32'h00000000;
 // synthesis translate_on 
 RAM32X1S stack_bit_2 ( 
 .D(pc[2]),
 .WE(stack_write_enable),
 .WCLK(clk),
 .A0(stack_address[0]),
 .A1(stack_address[1]),
 .A2(stack_address[2]),
 .A3(stack_address[3]),
 .A4(stack_address[4]),
 .O(stack_ram_data[2]))/* synthesis xc_props = "INIT=00000000"*/;

 FD stack_flop_2 ( 
 .D(stack_ram_data[2]),
 .Q(stack_pop_data[2]),
 .C(clk));
 
  // synthesis translate_off 
 defparam stack_bit_3.INIT = 32'h00000000;
 // synthesis translate_on 
 RAM32X1S stack_bit_3 ( 
 .D(pc[3]),
 .WE(stack_write_enable),
 .WCLK(clk),
 .A0(stack_address[0]),
 .A1(stack_address[1]),
 .A2(stack_address[2]),
 .A3(stack_address[3]),
 .A4(stack_address[4]),
 .O(stack_ram_data[3]))/* synthesis xc_props = "INIT=00000000"*/;

 FD stack_flop_3 ( 
 .D(stack_ram_data[3]),
 .Q(stack_pop_data[3]),
 .C(clk));
 
 // synthesis translate_off 
 defparam stack_bit_4.INIT = 32'h00000000;
 // synthesis translate_on 
 RAM32X1S stack_bit_4 ( 
 .D(pc[4]),
 .WE(stack_write_enable),
 .WCLK(clk),
 .A0(stack_address[0]),
 .A1(stack_address[1]),
 .A2(stack_address[2]),
 .A3(stack_address[3]),
 .A4(stack_address[4]),
 .O(stack_ram_data[4]))/* synthesis xc_props = "INIT=00000000"*/;

 FD stack_flop_4 ( 
 .D(stack_ram_data[4]),
 .Q(stack_pop_data[4]),
 .C(clk));

 // synthesis translate_off 
 defparam stack_bit_5.INIT = 32'h00000000;
 // synthesis translate_on 
 RAM32X1S stack_bit_5 ( 
 .D(pc[5]),
 .WE(stack_write_enable),
 .WCLK(clk),
 .A0(stack_address[0]),
 .A1(stack_address[1]),
 .A2(stack_address[2]),
 .A3(stack_address[3]),
 .A4(stack_address[4]),
 .O(stack_ram_data[5]))/* synthesis xc_props = "INIT=00000000"*/;

 FD stack_flop_5 ( 
 .D(stack_ram_data[5]),
 .Q(stack_pop_data[5]),
 .C(clk));

 // synthesis translate_off 
 defparam stack_bit_6.INIT = 32'h00000000;
 // synthesis translate_on 
 RAM32X1S stack_bit_6 ( 
 .D(pc[6]),
 .WE(stack_write_enable),
 .WCLK(clk),
 .A0(stack_address[0]),
 .A1(stack_address[1]),
 .A2(stack_address[2]),
 .A3(stack_address[3]),
 .A4(stack_address[4]),
 .O(stack_ram_data[6]))/* synthesis xc_props = "INIT=00000000"*/;

 FD stack_flop_6 ( 
 .D(stack_ram_data[6]),
 .Q(stack_pop_data[6]),
 .C(clk));

 // synthesis translate_off 
 defparam stack_bit_7.INIT = 32'h00000000;
 // synthesis translate_on 
 RAM32X1S stack_bit_7 ( 
 .D(pc[7]),
 .WE(stack_write_enable),
 .WCLK(clk),
 .A0(stack_address[0]),
 .A1(stack_address[1]),
 .A2(stack_address[2]),
 .A3(stack_address[3]),
 .A4(stack_address[4]),
 .O(stack_ram_data[7]))/* synthesis xc_props = "INIT=00000000"*/;

 FD stack_flop_7 ( 
 .D(stack_ram_data[7]),
 .Q(stack_pop_data[7]),
 .C(clk));

 // synthesis translate_off 
 defparam stack_bit_8.INIT = 32'h00000000;
 // synthesis translate_on 
 RAM32X1S stack_bit_8 ( 
 .D(pc[8]),
 .WE(stack_write_enable),
 .WCLK(clk),
 .A0(stack_address[0]),
 .A1(stack_address[1]),
 .A2(stack_address[2]),
 .A3(stack_address[3]),
 .A4(stack_address[4]),
 .O(stack_ram_data[8]))/* synthesis xc_props = "INIT=00000000"*/;

 FD stack_flop_8 ( 
 .D(stack_ram_data[8]),
 .Q(stack_pop_data[8]),
 .C(clk));

 // synthesis translate_off 
 defparam stack_bit_9.INIT = 32'h00000000;
 // synthesis translate_on 
 RAM32X1S stack_bit_9 ( 
 .D(pc[9]),
 .WE(stack_write_enable),
 .WCLK(clk),
 .A0(stack_address[0]),
 .A1(stack_address[1]),
 .A2(stack_address[2]),
 .A3(stack_address[3]),
 .A4(stack_address[4]),
 .O(stack_ram_data[9]))/* synthesis xc_props = "INIT=00000000"*/;

 FD stack_flop_9 ( 
 .D(stack_ram_data[9]),
 .Q(stack_pop_data[9]),
 .C(clk));
       
 // Stack address pointer is a 5-bit counter

 INV stack_count_inv( // Inverter should be implemented in the CE to the flip-flops
 .I(active_interrupt),
 .O(not_active_interrupt)); 

 //stack_count_loop 

 // synthesis translate_off 
 defparam count_lut_0.INIT = 16'h6555;
 // synthesis translate_on 
 LUT4 count_lut_0 ( 
 .I0(stack_address[0]),
 .I1(t_state),
 .I2(valid_to_move),
 .I3(push_or_pop_type),
 .O(half_stack_address[0]) )/* synthesis xc_props = "INIT=6555"*/;
 
 MUXCY count_muxcy_0 ( 
 .DI(stack_address[0]),
 .CI(1'b0),
 .S(half_stack_address[0]),
 .O(stack_address_carry[0]));
 
 XORCY count_xor_0 ( 
 .LI(half_stack_address[0]),
 .CI(1'b0),
 .O(next_stack_address[0]));

 FDRE stack_count_loop_register_bit_0 ( 
 .D(next_stack_address[0]),
 .Q(stack_address[0]),
 .R(internal_reset),
 .CE(not_active_interrupt),
 .C(clk));                   

 // synthesis translate_off 
 defparam count_lut_1.INIT = 16'hA999;
 // synthesis translate_on 
 LUT4 count_lut_1 ( 
 .I0(stack_address[1]),
 .I1(t_state),
 .I2(valid_to_move),
 .I3(call_type),
 .O(half_stack_address[1]) )/* synthesis xc_props = "INIT=A999"*/;
 
 MUXCY count_muxcy_1 ( 
 .DI(stack_address[1]),
 .CI(stack_address_carry[0]),
 .S(half_stack_address[1]),
 .O(stack_address_carry[1]));
 
 XORCY count_xor_1 ( 
 .LI(half_stack_address[1]),
 .CI(stack_address_carry[0]),
 .O(next_stack_address[1]));
                   
 FDRE stack_count_loop_register_bit_1 ( 
 .D(next_stack_address[1]),
 .Q(stack_address[1]),
 .R(internal_reset),
 .CE(not_active_interrupt),
 .C(clk));  

 // synthesis translate_off 
 defparam count_lut_2.INIT = 16'hA999;
 // synthesis translate_on 
 LUT4 count_lut_2 ( 
 .I0(stack_address[2]),
 .I1(t_state),
 .I2(valid_to_move),
 .I3(call_type),
 .O(half_stack_address[2]) )/* synthesis xc_props = "INIT=A999"*/;
 
 MUXCY count_muxcy_2 ( 
 .DI(stack_address[2]),
 .CI(stack_address_carry[1]),
 .S(half_stack_address[2]),
 .O(stack_address_carry[2]));
 
 XORCY count_xor_2 ( 
 .LI(half_stack_address[2]),
 .CI(stack_address_carry[1]),
 .O(next_stack_address[2]));
                   
 FDRE stack_count_loop_register_bit_2 ( 
 .D(next_stack_address[2]),
 .Q(stack_address[2]),
 .R(internal_reset),
 .CE(not_active_interrupt),
 .C(clk)); 

 // synthesis translate_off 
 defparam count_lut_3.INIT = 16'hA999;
 // synthesis translate_on 
 LUT4 count_lut_3 ( 
 .I0(stack_address[3]),
 .I1(t_state),
 .I2(valid_to_move),
 .I3(call_type),
 .O(half_stack_address[3]) )/* synthesis xc_props = "INIT=A999"*/;
 
 MUXCY count_muxcy_3 ( 
 .DI(stack_address[3]),
 .CI(stack_address_carry[2]),
 .S(half_stack_address[3]),
 .O(stack_address_carry[3]));
 
 XORCY count_xor_3 ( 
 .LI(half_stack_address[3]),
 .CI(stack_address_carry[2]),
 .O(next_stack_address[3]));
                   
 FDRE stack_count_loop_register_bit_3 ( 
 .D(next_stack_address[3]),
 .Q(stack_address[3]),
 .R(internal_reset),
 .CE(not_active_interrupt),
 .C(clk)); 

 // synthesis translate_off 
 defparam count_lut_4.INIT = 16'hA999;
 // synthesis translate_on 
 LUT4 count_lut_4 ( 
 .I0(stack_address[4]),
 .I1(t_state),
 .I2(valid_to_move),
 .I3(call_type),
 .O(half_stack_address[4]) )/* synthesis xc_props = "INIT=A999"*/;
 
 XORCY count_xor_4 ( 
 .LI(half_stack_address[4]),
 .CI(stack_address_carry[3]),
 .O(next_stack_address[4]));

 FDRE stack_count_loop_register_bit_4 ( 
 .D(next_stack_address[4]),
 .Q(stack_address[4]),
 .R(internal_reset),
 .CE(not_active_interrupt),
 .C(clk));
//
////////////////////////////////////////////////////////////////////////////////////
//
// End of description for KCPSM3 macro.
//
////////////////////////////////////////////////////////////////////////////////////
//
//**********************************************************************************
// Code for simulation purposes only after this line
//**********************************************************************************
//
////////////////////////////////////////////////////////////////////////////////////
//
// Code for simulation.
//
// Disassemble the instruction codes to form a text string for display.
// Determine status of reset and flags and present in the form of a text string.
// Provide local variables to simulate the contents of each register and scratch 
// pad memory location.
//
////////////////////////////////////////////////////////////////////////////////////
//
 //All of this section is ignored during synthesis.
 //synthesis translate_off
 //
 //complete instruction decode
 //
 reg  [1:152] kcpsm3_opcode ;
 //
 //Status of flags and processor
 //
 reg  [1:104] kcpsm3_status ;
 //
 //contents of each register
 //
 reg  [7:0] s0_contents ;
 reg  [7:0] s1_contents ;
 reg    [7:0] s2_contents ;
 reg    [7:0] s3_contents ;
 reg    [7:0] s4_contents ;
 reg    [7:0] s5_contents ;
 reg    [7:0] s6_contents ;
 reg    [7:0] s7_contents ;
 reg    [7:0] s8_contents ;
 reg    [7:0] s9_contents ;
 reg    [7:0] sa_contents ;
 reg    [7:0] sb_contents ;
 reg    [7:0] sc_contents ;
 reg    [7:0] sd_contents ;
 reg    [7:0] se_contents ;
 reg    [7:0] sf_contents ;
 //
 //contents of each scratch pad memory location
 // 
 reg  [7:0]   spm00_contents ;
 reg  [7:0]   spm01_contents ;
 reg  [7:0]   spm02_contents ;
 reg  [7:0]   spm03_contents ;
 reg  [7:0]   spm04_contents ;
 reg  [7:0]   spm05_contents ;
 reg  [7:0]   spm06_contents ;
 reg  [7:0]   spm07_contents ;
 reg  [7:0]   spm08_contents ;
 reg  [7:0]   spm09_contents ;
 reg  [7:0]   spm0a_contents ;
 reg  [7:0]   spm0b_contents ;
 reg  [7:0]   spm0c_contents ;
 reg  [7:0]   spm0d_contents ;
 reg  [7:0]   spm0e_contents ;
 reg  [7:0]   spm0f_contents ;
 reg  [7:0]   spm10_contents ;
 reg  [7:0]   spm11_contents ;
 reg  [7:0]   spm12_contents ;
 reg  [7:0]   spm13_contents ;
 reg  [7:0]   spm14_contents ;
 reg  [7:0]   spm15_contents ;
 reg  [7:0]   spm16_contents ;
 reg  [7:0]   spm17_contents ;
 reg  [7:0]   spm18_contents ;
 reg  [7:0]   spm19_contents ;
 reg  [7:0]   spm1a_contents ;
 reg  [7:0]   spm1b_contents ;
 reg  [7:0]   spm1c_contents ;
 reg  [7:0]   spm1d_contents ;
 reg  [7:0]   spm1e_contents ;
 reg  [7:0]   spm1f_contents ;
 reg  [7:0]   spm20_contents ;
 reg  [7:0]   spm21_contents ;
 reg  [7:0]   spm22_contents ;
 reg  [7:0]   spm23_contents ;
 reg  [7:0]   spm24_contents ;
 reg  [7:0]   spm25_contents ;
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Created:Tue Mar 14 03:42:57 2006
From: kcpsm3.v

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