reg [7:0] spm26_contents ;
reg [7:0] spm27_contents ;
reg [7:0] spm28_contents ;
reg [7:0] spm29_contents ;
reg [7:0] spm2a_contents ;
reg [7:0] spm2b_contents ;
reg [7:0] spm2c_contents ;
reg [7:0] spm2d_contents ;
reg [7:0] spm2e_contents ;
reg [7:0] spm2f_contents ;
reg [7:0] spm30_contents ;
reg [7:0] spm31_contents ;
reg [7:0] spm32_contents ;
reg [7:0] spm33_contents ;
reg [7:0] spm34_contents ;
reg [7:0] spm35_contents ;
reg [7:0] spm36_contents ;
reg [7:0] spm37_contents ;
reg [7:0] spm38_contents ;
reg [7:0] spm39_contents ;
reg [7:0] spm3a_contents ;
reg [7:0] spm3b_contents ;
reg [7:0] spm3c_contents ;
reg [7:0] spm3d_contents ;
reg [7:0] spm3e_contents ;
reg [7:0] spm3f_contents ;
// initialise the values
initial begin
kcpsm3_status = "NZ, NC, Reset";
s0_contents = 8'h00 ;
s1_contents = 8'h00 ;
s2_contents = 8'h00 ;
s3_contents = 8'h00 ;
s4_contents = 8'h00 ;
s5_contents = 8'h00 ;
s6_contents = 8'h00 ;
s7_contents = 8'h00 ;
s8_contents = 8'h00 ;
s9_contents = 8'h00 ;
sa_contents = 8'h00 ;
sb_contents = 8'h00 ;
sc_contents = 8'h00 ;
sd_contents = 8'h00 ;
se_contents = 8'h00 ;
sf_contents = 8'h00 ;
spm00_contents = 8'h00 ;
spm01_contents = 8'h00 ;
spm02_contents = 8'h00 ;
spm03_contents = 8'h00 ;
spm04_contents = 8'h00 ;
spm05_contents = 8'h00 ;
spm06_contents = 8'h00 ;
spm07_contents = 8'h00 ;
spm08_contents = 8'h00 ;
spm09_contents = 8'h00 ;
spm0a_contents = 8'h00 ;
spm0b_contents = 8'h00 ;
spm0c_contents = 8'h00 ;
spm0d_contents = 8'h00 ;
spm0e_contents = 8'h00 ;
spm0f_contents = 8'h00 ;
spm10_contents = 8'h00 ;
spm11_contents = 8'h00 ;
spm12_contents = 8'h00 ;
spm13_contents = 8'h00 ;
spm14_contents = 8'h00 ;
spm15_contents = 8'h00 ;
spm16_contents = 8'h00 ;
spm17_contents = 8'h00 ;
spm18_contents = 8'h00 ;
spm19_contents = 8'h00 ;
spm1a_contents = 8'h00 ;
spm1b_contents = 8'h00 ;
spm1c_contents = 8'h00 ;
spm1d_contents = 8'h00 ;
spm1e_contents = 8'h00 ;
spm1f_contents = 8'h00 ;
spm20_contents = 8'h00 ;
spm21_contents = 8'h00 ;
spm22_contents = 8'h00 ;
spm23_contents = 8'h00 ;
spm24_contents = 8'h00 ;
spm25_contents = 8'h00 ;
spm26_contents = 8'h00 ;
spm27_contents = 8'h00 ;
spm28_contents = 8'h00 ;
spm29_contents = 8'h00 ;
spm2a_contents = 8'h00 ;
spm2b_contents = 8'h00 ;
spm2c_contents = 8'h00 ;
spm2d_contents = 8'h00 ;
spm2e_contents = 8'h00 ;
spm2f_contents = 8'h00 ;
spm30_contents = 8'h00 ;
spm31_contents = 8'h00 ;
spm32_contents = 8'h00 ;
spm33_contents = 8'h00 ;
spm34_contents = 8'h00 ;
spm35_contents = 8'h00 ;
spm36_contents = 8'h00 ;
spm37_contents = 8'h00 ;
spm38_contents = 8'h00 ;
spm39_contents = 8'h00 ;
spm3a_contents = 8'h00 ;
spm3b_contents = 8'h00 ;
spm3c_contents = 8'h00 ;
spm3d_contents = 8'h00 ;
spm3e_contents = 8'h00 ;
spm3f_contents = 8'h00 ;
end
//
//
wire [1:16] sx_decode ; //sX register specification
wire [1:16] sy_decode ; //sY register specification
wire [1:16] kk_decode ; //constant value specification
wire [1:24] aaa_decode ; //address specification
//
////////////////////////////////////////////////////////////////////////////////
//
// Function to convert 4-bit binary nibble to hexadecimal character
//
////////////////////////////////////////////////////////////////////////////////
//
function [1:8] hexcharacter ;
input [3:0] nibble ;
begin
case (nibble)
4'b0000 : hexcharacter = "0" ;
4'b0001 : hexcharacter = "1" ;
4'b0010 : hexcharacter = "2" ;
4'b0011 : hexcharacter = "3" ;
4'b0100 : hexcharacter = "4" ;
4'b0101 : hexcharacter = "5" ;
4'b0110 : hexcharacter = "6" ;
4'b0111 : hexcharacter = "7" ;
4'b1000 : hexcharacter = "8" ;
4'b1001 : hexcharacter = "9" ;
4'b1010 : hexcharacter = "A" ;
4'b1011 : hexcharacter = "B" ;
4'b1100 : hexcharacter = "C" ;
4'b1101 : hexcharacter = "D" ;
4'b1110 : hexcharacter = "E" ;
4'b1111 : hexcharacter = "F" ;
endcase
end
endfunction
/*
//
////////////////////////////////////////////////////////////////////////////////
//
begin
*/
// decode first register
assign sx_decode[1:8] = "s" ;
assign sx_decode[9:16] = hexcharacter(instruction[11:8]) ;
// decode second register
assign sy_decode[1:8] = "s";
assign sy_decode[9:16] = hexcharacter(instruction[7:4]);
// decode constant value
assign kk_decode[1:8] = hexcharacter(instruction[7:4]);
assign kk_decode[9:16] = hexcharacter(instruction[3:0]);
// address value
assign aaa_decode[1:8] = hexcharacter({2'b00, instruction[9:8]});
assign aaa_decode[9:16] = hexcharacter(instruction[7:4]);
assign aaa_decode[17:24] = hexcharacter(instruction[3:0]);
// decode instruction
always @ (instruction or kk_decode or sy_decode or sx_decode or aaa_decode)
begin
case (instruction[17:12])
6'b000000 : begin kcpsm3_opcode <= {"LOAD ", sx_decode, ",", kk_decode, " "} ; end
6'b000001 : begin kcpsm3_opcode <= {"LOAD ", sx_decode, ",", sy_decode, " "} ; end
6'b001010 : begin kcpsm3_opcode <= {"AND ", sx_decode, ",", kk_decode, " "} ; end
6'b001011 : begin kcpsm3_opcode <= {"AND ", sx_decode, ",", sy_decode, " "} ; end
6'b001100 : begin kcpsm3_opcode <= {"OR ", sx_decode, ",", kk_decode, " "} ; end
6'b001101 : begin kcpsm3_opcode <= {"OR ", sx_decode, ",", sy_decode, " "} ; end
6'b001110 : begin kcpsm3_opcode <= {"XOR ", sx_decode, ",", kk_decode, " "} ; end
6'b001111 : begin kcpsm3_opcode <= {"XOR ", sx_decode, ",", sy_decode, " "} ; end
6'b010010 : begin kcpsm3_opcode <= {"TEST ", sx_decode, ",", kk_decode, " "} ; end
6'b010011 : begin kcpsm3_opcode <= {"TEST ", sx_decode, ",", sy_decode, " "} ; end
6'b011000 : begin kcpsm3_opcode <= {"ADD ", sx_decode, ",", kk_decode, " "} ; end
6'b011001 : begin kcpsm3_opcode <= {"ADD ", sx_decode, ",", sy_decode, " "} ; end
6'b011010 : begin kcpsm3_opcode <= {"ADDCY", sx_decode, ",", kk_decode, " "} ; end
6'b011011 : begin kcpsm3_opcode <= {"ADDCY", sx_decode, ",", sy_decode, " "} ; end
6'b011100 : begin kcpsm3_opcode <= {"SUB ", sx_decode, ",", kk_decode, " "} ; end
6'b011101 : begin kcpsm3_opcode <= {"SUB ", sx_decode, ",", sy_decode, " "} ; end
6'b011110 : begin kcpsm3_opcode <= {"SUBCY", sx_decode, ",", kk_decode, " "} ; end
6'b011111 : begin kcpsm3_opcode <= {"SUBCY", sx_decode, ",", sy_decode, " "} ; end
6'b010100 : begin kcpsm3_opcode <= {"COMPARE ", sx_decode, ",", kk_decode, " "} ; end
6'b010101 : begin kcpsm3_opcode <= {"COMPARE ", sx_decode, ",", sy_decode, " "} ; end
6'b100000 : begin
case (instruction[3:0])
4'b0110 : begin kcpsm3_opcode <= {"SL0 ", sx_decode, " "}; end
4'b0111 : begin kcpsm3_opcode <= {"SL1 ", sx_decode, " "}; end
4'b0100 : begin kcpsm3_opcode <= {"SLX ", sx_decode, " "}; end
4'b0000 : begin kcpsm3_opcode <= {"SLA ", sx_decode, " "}; end
4'b0010 : begin kcpsm3_opcode <= {"RL ", sx_decode, " "}; end
4'b1110 : begin kcpsm3_opcode <= {"SR0 ", sx_decode, " "}; end
4'b1111 : begin kcpsm3_opcode <= {"SR1 ", sx_decode, " "}; end
4'b1010 : begin kcpsm3_opcode <= {"SRX ", sx_decode, " "}; end
4'b1000 : begin kcpsm3_opcode <= {"SRA ", sx_decode, " "}; end
4'b1100 : begin kcpsm3_opcode <= {"RR ", sx_decode, " "}; end
default : begin kcpsm3_opcode <= "Invalid Instruction"; end
endcase
end
6'b101100 : begin kcpsm3_opcode <= {"OUTPUT ", sx_decode, ",", kk_decode, " "}; end
6'b101101 : begin kcpsm3_opcode <= {"OUTPUT ", sx_decode, ",(", sy_decode, ") "}; end
6'b000100 : begin kcpsm3_opcode <= {"INPUT ", sx_decode, ",", kk_decode, " "}; end
6'b000101 : begin kcpsm3_opcode <= {"INPUT ", sx_decode, ",(", sy_decode, ") "}; end
6'b101110 : begin kcpsm3_opcode <= {"STORE ", sx_decode, ",", kk_decode, " "}; end
6'b101111 : begin kcpsm3_opcode <= {"STORE ", sx_decode, ",(", sy_decode, ") "}; end
6'b000110 : begin kcpsm3_opcode <= {"FETCH ", sx_decode, ",", kk_decode, " "}; end
6'b000111 : begin kcpsm3_opcode <= {"FETCH ", sx_decode, ",(", sy_decode, ") "}; end
6'b110100 : begin kcpsm3_opcode <= {"JUMP ", aaa_decode, " "}; end
6'b110101 : begin
case (instruction[11:10])
2'b00 : begin kcpsm3_opcode <= {"JUMP Z,", aaa_decode, " "}; end
2'b01 : begin kcpsm3_opcode <= {"JUMP NZ,", aaa_decode, " "}; end
2'b10 : begin kcpsm3_opcode <= {"JUMP C,", aaa_decode, " "}; end
2'b11 : begin kcpsm3_opcode <= {"JUMP NC,", aaa_decode, " "}; end
default : begin kcpsm3_opcode <= "Invalid Instruction"; end
endcase
end
6'b110000 : begin kcpsm3_opcode <= {"CALL ", aaa_decode, " "}; end
6'b110001 : begin
case (instruction[11:10])
2'b00 : begin kcpsm3_opcode <= {"CALL Z,", aaa_decode, " "}; end
2'b01 : begin kcpsm3_opcode <= {"CALL NZ,", aaa_decode, " "}; end
2'b10 : begin kcpsm3_opcode <= {"CALL C,", aaa_decode, " "}; end
2'b11 : begin kcpsm3_opcode <= {"CALL NC,", aaa_decode, " "}; end
default : begin kcpsm3_opcode <= "Invalid Instruction"; end
endcase
end
6'b101010 : begin kcpsm3_opcode <= "RETURN "; end
6'b101011 : begin
case (instruction[11:10])
2'b00 : begin kcpsm3_opcode <= "RETURN Z "; end
2'b01 : begin kcpsm3_opcode <= "RETURN NZ "; end
2'b10 : begin kcpsm3_opcode <= "RETURN C "; end
2'b11 : begin kcpsm3_opcode <= "RETURN NC "; end
default : begin kcpsm3_opcode <= "Invalid Instruction"; end
endcase
end
6'b111000 : begin
case (instruction[0])
1'b0 : begin kcpsm3_opcode <= "RETURNI DISABLE "; end
1'b1 : begin kcpsm3_opcode <= "RETURNI ENABLE "; end
default : begin kcpsm3_opcode <= "Invalid Instruction"; end
endcase
end
6'b111100 : begin
case (instruction[0])
1'b0 : begin kcpsm3_opcode <= "DISABLE INTERRUPT "; end
1'b1 : begin kcpsm3_opcode <= "ENABLE INTERRUPT "; end
default : begin kcpsm3_opcode <= "Invalid Instruction"; end
endcase
end
default : begin kcpsm3_opcode <= "Invalid Instruction"; end
endcase
end
//reset and flag status information
always @ (posedge clk) begin
if (reset==1'b1 || reset_delay==1'b1) begin
kcpsm3_status = "NZ, NC, Reset";
end
else begin
kcpsm3_status[65:104] <= " ";
if (flag_enable == 1'b1) begin
if (zero_carry == 1'b1) begin
kcpsm3_status[1:32] <= " Z, ";
end
else begin
kcpsm3_status[1:32] <= "NZ, ";
end
if (sel_carry[3] == 1'b1) begin
kcpsm3_status[33:48] <= " C";
end
else begin
kcpsm3_status[33:48] <= "NC";
end
end
end
end
//simulation of register contents
always @ (posedge clk) begin
if (register_enable == 1'b1) begin
case (instruction[11:8])
4'b0000 : begin s0_contents <= alu_result; end
4'b0001 : begin s1_contents <= alu_result; end
4'b0010 : begin s2_contents <= alu_result; end
4'b0011 : begin s3_contents <= alu_result; end
4'b0100 : begin s4_contents <= alu_result; end
4'b0101 : begin s5_contents <= alu_result; end
4'b0110 : begin s6_contents <= alu_result; end
4'b0111 : begin s7_contents <= alu_result; end
4'b1000 : begin s8_contents <= alu_result; end
4'b1001 : begin s9_contents <= alu_result; end
4'b1010 : begin sa_contents <= alu_result; end
4'b1011 : begin sb_contents <= alu_result; end
4'b1100 : begin sc_contents <= alu_result; end
4'b1101 : begin sd_contents <= alu_result; end
4'b1110 : begin se_contents <= alu_result; end
default : begin sf_contents <= alu_result; end
endcase
end
end
//simulation of scratch pad memory contents
always @ (posedge clk) begin
if (memory_enable==1'b1) begin
case (second_operand[5:0])
6'b000000 : begin spm00_contents <= sx ; end
6'b000001 : begin spm01_contents <= sx ; end
6'b000010 : begin spm02_contents <= sx ; end
6'b000011 : begin spm03_contents <= sx ; end
6'b000100 : begin spm04_contents <= sx ; end
6'b000101 : begin spm05_contents <= sx ; end
6'b000110 : begin spm06_contents <= sx ; end
6'b000111 : begin spm07_contents <= sx ; end
6'b001000 : begin spm08_contents <= sx ; end
6'b001001 : begin spm09_contents <= sx ; end
6'b001010 : begin spm0a_contents <= sx ; end
6'b001011 : begin spm0b_contents <= sx ; end
6'b001100 : begin spm0c_contents <= sx ; end
6'b001101 : begin spm0d_contents <= sx ; end
6'b001110 : begin spm0e_contents <= sx ; end
6'b001111 : begin spm0f_contents <= sx ; end
6'b010000 : begin spm10_contents <= sx ; end
6'b010001 : begin spm11_contents <= sx ; end
6'b010010 : begin spm12_contents <= sx ; end
6'b010011 : begin spm13_contents <= sx ; end
6'b010100 : begin spm14_contents <= sx ; end
6'b010101 : begin spm15_contents <= sx ; end
6'b010110 : begin spm16_contents <= sx ; end
6'b010111 : begin spm17_contents <= sx ; end
6'b011000 : begin spm18_contents <= sx ; end
6'b011001 : begin spm19_contents <= sx ; end
6'b011010 : begin spm1a_contents <= sx ; end
6'b011011 : begin spm1b_contents <= sx ; end
6'b011100 : begin spm1c_contents <= sx ; end
6'b011101 : begin spm1d_contents <= sx ; end
6'b011110 : begin spm1e_contents <= sx ; end
6'b011111 : begin spm1f_contents <= sx ; end
6'b100000 : begin spm20_contents <= sx ; end
6'b100001 : begin spm21_contents <= sx ; end
6'b100010 : begin spm22_contents <= sx ; end
6'b100011 : begin spm23_contents <= sx ; end
6'b100100 : begin spm24_contents <= sx ; end
6'b100101 : begin spm25_contents <= sx ; end
6'b100110 : begin spm26_contents <= sx ; end
6'b100111 : begin spm27_contents <= sx ; end
6'b101000 : begin spm28_contents <= sx ; end
6'b101001 : begin spm29_contents <= sx ; end
6'b101010 : begin spm2a_contents <= sx ; end
6'b101011 : begin spm2b_contents <= sx ; end
6'b101100 : begin spm2c_contents <= sx ; end
6'b101101 : begin spm2d_contents <= sx ; end
6'b101110 : begin spm2e_contents <= sx ; end
6'b101111 : begin spm2f_contents <= sx ; end
6'b110000 : begin spm30_contents <= sx ; end
6'b110001 : begin spm31_contents <= sx ; end
6'b110010 : begin spm32_contents <= sx ; end
6'b110011 : begin spm33_contents <= sx ; end
6'b110100 : begin spm34_contents <= sx ; end
6'b110101 : begin spm35_contents <= sx ; end
6'b110110 : begin spm36_contents <= sx ; end
6'b110111 : begin spm37_contents <= sx ; end
6'b111000 : begin spm38_contents <= sx ; end
6'b111001 : begin spm39_contents <= sx ; end
6'b111010 : begin spm3a_contents <= sx ; end
6'b111011 : begin spm3b_contents <= sx ; end
6'b111100 : begin spm3c_contents <= sx ; end
6'b111101 : begin spm3d_contents <= sx ; end
6'b111110 : begin spm3e_contents <= sx ; end
default : begin spm3f_contents <= sx ; end
endcase
end
end
//**********************************************************************************
// End of simulation code.
//**********************************************************************************
//synthesis translate_on
////////////////////////////////////////////////////////////////////////////////////
//
// END OF FILE KCPSM3.V
//
////////////////////////////////////////////////////////////////////////////////////
//
endmodule