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////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2004 Xilinx, Inc.
// All Rights Reserved
////////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: 1.30
//  \   \         Filename: kcpsm3.v
//  /   /         Date Last Modified:  August 5 2004
// /___/   /\     Date Created: May 19 2003
// \   \  /  \
//  \___\/\___\
//
//Device:   Xilinx
//Purpose:  
// Constant (K) Coded Programmable State Machine for Spartan-3 Devices.
// Also suitable for use with Virtex-II and Virtex-IIPRO devices.
//
// Includes additional code for enhanced verilog simulation. 
//
// Instruction disassembly concept inspired by the work of Prof. Dr.-Ing. Bernhard Lang.
// University of Applied Sciences, Osnabrueck, Germany.
//
// Format of this file.
//  --------------------
// This file contains the definition of KCPSM3 as one complete module This 'flat' 
// approach has been adopted to decrease 
// the time taken to load the module into simulators and the synthesis process.
//
// The module defines the implementation of the logic using Xilinx primitives.
// These ensure predictable synthesis results and maximise the density of the implementation. 
//
//Reference:
//  None
//Revision History:
//    Rev 1.00 - kc -  Start of design entry,  May 19 2003.
//    Rev 1.20 - njs - Converted to verilog,  July 20 2004.
//    Verilog version creation supported by Chip Lukes, 
//    Advanced Electronic Designs, Inc.
//    www.aedbozeman.com,
//    chip.lukes@aedmt.com
//  Rev 1.21 - sus - Added text to adhere to HDL standard, August 4 2004. 
//  Rev 1.30 - njs - Updated as per VHDL version 1.30 August 5 2004. 
//
////////////////////////////////////////////////////////////////////////////////
// Contact: e-mail  picoblaze@xilinx.com
//////////////////////////////////////////////////////////////////////////////////
//
// Disclaimer: 
// LIMITED WARRANTY AND DISCLAIMER. These designs are
// provided to you "as is". Xilinx and its licensors make and you
// receive no warranties or conditions, express, implied,
// statutory or otherwise, and Xilinx specifically disclaims any
// implied warranties of merchantability, non-infringement, or
// fitness for a particular purpose. Xilinx does not warrant that
// the functions contained in these designs will meet your
// requirements, or that the operation of these designs will be
// uninterrupted or error free, or that defects in the Designs
// will be corrected. Furthermore, Xilinx does not warrant or
// make any representations regarding use or the results of the
// use of the designs in terms of correctness, accuracy,
// reliability, or otherwise.
//
// LIMITATION OF LIABILITY. In no event will Xilinx or its
// licensors be liable for any loss of data, lost profits, cost
// or procurement of substitute goods or services, or for any
// special, incidental, consequential, or indirect damages
// arising from the use or operation of the designs or
// accompanying documentation, however caused and on any theory
// of liability. This limitation will apply even if Xilinx
// has been advised of the possibility of such damage. This
// limitation shall apply not-withstanding the failure of the 
// essential purpose of any limited remedies herein. 
//////////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1ps

[Up: compare3_tb dut_1]
module kcpsm3Index(
  address,
  instruction,
  port_id,
  write_strobe,
  out_port,
  read_strobe,
  in_port,
  interrupt,
  interrupt_ack,
  reset,
  clk) ;
 
output  [9:0] address ;
input   [17:0]  instruction ;
output  [7:0] port_id ;
output    write_strobe, read_strobe, interrupt_ack ;
output  [7:0] out_port ;
input   [7:0] in_port ;
input   interrupt, reset, clk ;
//
////////////////////////////////////////////////////////////////////////////////////
//
// Start of Main Architecture for KCPSM3
//
////////////////////////////////////////////////////////////////////////////////////
//
// Signals used in KCPSM3
//
////////////////////////////////////////////////////////////////////////////////////
//
// Fundamental control and decode signals
//   
wire    t_state ;
wire    not_t_state ;
wire    internal_reset ;
wire    reset_delay ;
wire    move_group ;
wire    condition_met ;
wire    normal_count ;
wire    call_type ;
wire    push_or_pop_type ;
wire    valid_to_move ;
//
// Flag signals
// 
wire    flag_type ;
wire    flag_write ;
wire    flag_enable ;
wire    zero_flag ;
wire    sel_shadow_zero ;
wire    low_zero ;
wire    high_zero ;
wire    low_zero_carry ;
wire    high_zero_carry ;
wire    zero_carry ;
wire    zero_fast_route ;
wire    low_parity ;
wire    high_parity ;
wire    parity_carry ;
wire    parity ;
wire    carry_flag ;
wire    sel_parity ;
wire    sel_arith_carry ;
wire    sel_shift_carry ;
wire    sel_shadow_carry ;
wire  [3:0] sel_carry ;
wire    carry_fast_route ;
//
// Interrupt signals
// 
wire    active_interrupt ;
wire    int_pulse ;
wire    clean_int ;
wire    shadow_carry ;
wire    shadow_zero ;
wire    int_enable ;
wire    int_update_enable ;
wire    int_enable_value ;
wire    interrupt_ack_internal ;
//
// Program Counter signals
//
wire  [9:0] pc ;
wire  [9:0] pc_vector ;
wire  [8:0] pc_vector_carry ;
wire  [9:0] inc_pc_vector ;
wire  [9:0] pc_value ;
wire  [8:0] pc_value_carry ;
wire  [9:0] inc_pc_value ;
wire    pc_enable ;
//
// Data Register signals
//
wire  [7:0] sx ;
wire  [7:0] sy ;
wire    register_type ;
wire    register_write ;
wire    register_enable ;
wire  [7:0] second_operand ;
//
// Scratch Pad Memory signals
//
wire  [7:0] memory_data ;
wire  [7:0] store_data ;
wire    memory_type ;
wire    memory_write ;
wire    memory_enable ;
//
// Stack signals
//
wire  [9:0] stack_pop_data ;
wire  [9:0] stack_ram_data ;
wire  [4:0] stack_address ;
wire  [4:0] half_stack_address ;
wire  [3:0] stack_address_carry ;
wire  [4:0] next_stack_address ;
wire    stack_write_enable ;
wire    not_active_interrupt ;
//
// ALU signals
//
wire  [7:0] logical_result ;
wire  [7:0] logical_value ;
wire    sel_logical ;
wire  [7:0] shift_result ;
wire  [7:0] shift_value ;
wire    sel_shift ;
wire    high_shift_in ;
wire    low_shift_in ;
wire    shift_in ;
wire    shift_carry ;
wire    shift_carry_value ;
wire  [7:0] arith_result ;
wire  [7:0] arith_value ;
wire  [7:0] half_arith ;
wire  [7:0] arith_internal_carry ;
wire    sel_arith_carry_in ;
wire    arith_carry_in ;
wire    invert_arith_carry ;
wire    arith_carry_out ;
wire    sel_arith ;
wire    arith_carry ;
//
// ALU multiplexer signals
//
wire    input_fetch_type ;
wire    sel_group ;
wire  [7:0] alu_group ;
wire  [7:0] input_group ;
wire  [7:0] alu_result ;
//
// read and write strobes 
//
wire    io_initial_decode ;
wire    write_active ;
wire    read_active ;
//
//
////////////////////////////////////////////////////////////////////////////////////
//
// XST attributes (Synplicity attributes are inline)

//synthesis attribute INIT of t_state_lut "1"; 
//synthesis attribute INIT of int_pulse_lut "0080";
//synthesis attribute INIT of int_update_lut "EAAA";
//synthesis attribute INIT of int_value_lut "04";
//synthesis attribute INIT of move_group_lut "7400";
//synthesis attribute INIT of condition_met_lut "5A3C";
//synthesis attribute INIT of normal_count_lut "2F";
//synthesis attribute INIT of call_type_lut "1000";
//synthesis attribute INIT of push_pop_lut "5400";
//synthesis attribute INIT of valid_move_lut "D";
//synthesis attribute INIT of flag_type_lut "41FC";
//synthesis attribute INIT of flag_enable_lut "8";
//synthesis attribute INIT of low_zero_lut "0001";
//synthesis attribute INIT of high_zero_lut "0001";
//synthesis attribute INIT of sel_shadow_zero_lut "3F";
//synthesis attribute INIT of low_parity_lut "6996";
//synthesis attribute INIT of high_parity_lut "6996";
//synthesis attribute INIT of sel_parity_lut "F3FF";
//synthesis attribute INIT of sel_arith_carry_lut "F3";
//synthesis attribute INIT of sel_shift_carry_lut "C";
//synthesis attribute INIT of sel_shadow_carry_lut "3";
//synthesis attribute INIT of register_type_lut "0145";
//synthesis attribute INIT of register_enable_lut "8";
//synthesis attribute INIT of memory_type_lut "0400";
//synthesis attribute INIT of memory_enable_lut "8000";
//synthesis attribute INIT of sel_logical_lut "FFE2";
//synthesis attribute INIT of low_shift_in_lut "E4";
//synthesis attribute INIT of high_shift_in_lut "E4";
//synthesis attribute INIT of shift_carry_lut "E4";
//synthesis attribute INIT of sel_arith_lut "1F";
//synthesis attribute INIT of input_fetch_type_lut "0002";
//synthesis attribute INIT of io_decode_lut "0010";
//synthesis attribute INIT of write_active_lut "4000";
//synthesis attribute INIT of read_active_lut "0100";
//
//synthesis attribute INIT of vector_select_mux_0 "E4";
//synthesis attribute INIT of vector_select_mux_1 "E4";
//synthesis attribute INIT of vector_select_mux_2 "E4";
//synthesis attribute INIT of vector_select_mux_3 "E4";
//synthesis attribute INIT of vector_select_mux_4 "E4";
//synthesis attribute INIT of vector_select_mux_5 "E4";
//synthesis attribute INIT of vector_select_mux_6 "E4";
//synthesis attribute INIT of vector_select_mux_7 "E4";
//synthesis attribute INIT of vector_select_mux_8 "E4";
//synthesis attribute INIT of vector_select_mux_9 "E4";
//synthesis attribute INIT of value_select_mux_0 "E4";
//synthesis attribute INIT of value_select_mux_1 "E4";
//synthesis attribute INIT of value_select_mux_2 "E4";
//synthesis attribute INIT of value_select_mux_3 "E4";
//synthesis attribute INIT of value_select_mux_4 "E4";
//synthesis attribute INIT of value_select_mux_5 "E4";
//synthesis attribute INIT of value_select_mux_6 "E4";
//synthesis attribute INIT of value_select_mux_7 "E4";
//synthesis attribute INIT of value_select_mux_8 "E4";
//synthesis attribute INIT of value_select_mux_9 "E4";
//
//synthesis attribute INIT of reg_loop_register_bit_0 "0000"; 
//synthesis attribute INIT of reg_loop_register_bit_1 "0000"; 
//synthesis attribute INIT of reg_loop_register_bit_2 "0000"; 
//synthesis attribute INIT of reg_loop_register_bit_3 "0000"; 
//synthesis attribute INIT of reg_loop_register_bit_4 "0000"; 
//synthesis attribute INIT of reg_loop_register_bit_5 "0000"; 
//synthesis attribute INIT of reg_loop_register_bit_6 "0000"; 
//synthesis attribute INIT of reg_loop_register_bit_7 "0000"; 
//synthesis attribute INIT of operand_select_mux_0 "E4"; 
//synthesis attribute INIT of operand_select_mux_1 "E4"; 
//synthesis attribute INIT of operand_select_mux_2 "E4"; 
//synthesis attribute INIT of operand_select_mux_3 "E4"; 
//synthesis attribute INIT of operand_select_mux_4 "E4"; 
//synthesis attribute INIT of operand_select_mux_5 "E4"; 
//synthesis attribute INIT of operand_select_mux_6 "E4"; 
//synthesis attribute INIT of operand_select_mux_7 "E4"; 
//
//synthesis attribute INIT of memory_bit_0 "0000000000000000"; 
//synthesis attribute INIT of memory_bit_1 "0000000000000000"; 
//synthesis attribute INIT of memory_bit_2 "0000000000000000"; 
//synthesis attribute INIT of memory_bit_3 "0000000000000000"; 
//synthesis attribute INIT of memory_bit_4 "0000000000000000"; 
//synthesis attribute INIT of memory_bit_5 "0000000000000000"; 
//synthesis attribute INIT of memory_bit_6 "0000000000000000"; 
//synthesis attribute INIT of memory_bit_7 "0000000000000000"; 
//
//synthesis attribute INIT of logical_lut_0 "6E8A"; 
//synthesis attribute INIT of logical_lut_1 "6E8A"; 
//synthesis attribute INIT of logical_lut_2 "6E8A"; 
//synthesis attribute INIT of logical_lut_3 "6E8A"; 
//synthesis attribute INIT of logical_lut_4 "6E8A"; 
//synthesis attribute INIT of logical_lut_5 "6E8A"; 
//synthesis attribute INIT of logical_lut_6 "6E8A"; 
//synthesis attribute INIT of logical_lut_7 "6E8A"; 
//
//synthesis attribute INIT of shift_mux_lut_0 "E4"; 
//synthesis attribute INIT of shift_mux_lut_1 "E4"; 
//synthesis attribute INIT of shift_mux_lut_2 "E4"; 
//synthesis attribute INIT of shift_mux_lut_3 "E4"; 
//synthesis attribute INIT of shift_mux_lut_4 "E4"; 
//synthesis attribute INIT of shift_mux_lut_5 "E4"; 
//synthesis attribute INIT of shift_mux_lut_6 "E4"; 
//synthesis attribute INIT of shift_mux_lut_7 "E4"; 

//synthesis attribute INIT of arith_carry_in_lut "6C"; 
//synthesis attribute INIT of arith_carry_out_lut "2"; 
//synthesis attribute INIT of arith_lut_0 "96"; 
//synthesis attribute INIT of arith_lut_1 "96"; 
//synthesis attribute INIT of arith_lut_2 "96"; 
//synthesis attribute INIT of arith_lut_3 "96"; 
//synthesis attribute INIT of arith_lut_4 "96"; 
//synthesis attribute INIT of arith_lut_5 "96"; 
//synthesis attribute INIT of arith_lut_6 "96"; 
//synthesis attribute INIT of arith_lut_7 "96"; 
//
//synthesis attribute INIT of or_lut_0 "FE"; 
//synthesis attribute INIT of or_lut_1 "FE"; 
//synthesis attribute INIT of or_lut_2 "FE"; 
//synthesis attribute INIT of or_lut_3 "FE"; 
//synthesis attribute INIT of or_lut_4 "FE"; 
//synthesis attribute INIT of or_lut_5 "FE"; 
//synthesis attribute INIT of or_lut_6 "FE"; 
//synthesis attribute INIT of or_lut_7 "FE"; 
//
//synthesis attribute INIT of mux_lut_0 "E4"; 
//synthesis attribute INIT of mux_lut_1 "E4"; 
//synthesis attribute INIT of mux_lut_2 "E4"; 
//synthesis attribute INIT of mux_lut_3 "E4"; 
//synthesis attribute INIT of mux_lut_4 "E4"; 
//synthesis attribute INIT of mux_lut_5 "E4"; 
//synthesis attribute INIT of mux_lut_6 "E4"; 
//synthesis attribute INIT of mux_lut_7 "E4"; 
//
//synthesis attribute INIT of stack_bit_0 "00000000"; 
//synthesis attribute INIT of stack_bit_1 "00000000"; 
//synthesis attribute INIT of stack_bit_2 "00000000"; 
//synthesis attribute INIT of stack_bit_3 "00000000"; 
//synthesis attribute INIT of stack_bit_4 "00000000"; 
//synthesis attribute INIT of stack_bit_5 "00000000"; 
//synthesis attribute INIT of stack_bit_6 "00000000"; 
//synthesis attribute INIT of stack_bit_7 "00000000"; 
//synthesis attribute INIT of stack_bit_8 "00000000"; 
//synthesis attribute INIT of stack_bit_9 "00000000"; 
//
//synthesis attribute INIT of count_lut_0 "6555"; 
//synthesis attribute INIT of count_lut_1 "A999"; 
//synthesis attribute INIT of count_lut_2 "A999"; 
//synthesis attribute INIT of count_lut_3 "A999"; 
//synthesis attribute INIT of count_lut_4 "A999"; 

////////////////////////////////////////////////////////////////////////////////////
//
// Start of KCPSM3 circuit description
//
////////////////////////////////////////////////////////////////////////////////////
//
// Fundamental Control
//
// Definition of T-state and internal reset
//
////////////////////////////////////////////////////////////////////////////////////
//
 // synthesis translate_off 
 defparam t_state_lut.INIT = 2'h1 ;
 // synthesis translate_on 
 LUT1 t_state_lut( 
 .I0(t_state),
 .O(not_t_state))/* synthesis xc_props = "INIT=1"*/;

 FDR toggle_flop ( 
 .D(not_t_state),
 .Q(t_state),
 .R(internal_reset),
 .C(clk));

 FDS reset_flop1 ( 
 .D(1'b0),
 .Q(reset_delay),
 .S(reset),
 .C(clk));

 FDS reset_flop2 ( 
 .D(reset_delay),
 .Q(internal_reset),
 .S(reset),
 .C(clk));
//
////////////////////////////////////////////////////////////////////////////////////
//
// Interrupt input logic, Interrupt enable and shadow Flags.
//  
// Captures interrupt input and enables the shadow flags.
// Decodes instructions which set and reset the interrupt enable flip-flop. 
//
////////////////////////////////////////////////////////////////////////////////////
//
 // Interrupt capture

 FDR int_capture_flop ( 
 .D(interrupt),
 .Q(clean_int),
 .R(internal_reset),
 .C(clk));

 // synthesis translate_off 
 defparam int_pulse_lut.INIT = 16'h0080 ;
 // synthesis translate_on 
 LUT4 int_pulse_lut ( 
 .I0(t_state),
 .I1(clean_int),
 .I2(int_enable),
 .I3(active_interrupt),
 .O(int_pulse ))/* synthesis xc_props = "INIT=0080"*/;

 FDR int_flop ( 
 .D(int_pulse),
 .Q(active_interrupt),
 .R(internal_reset),
 .C(clk));

 FD ack_flop ( 
 .D(active_interrupt),
 .Q(interrupt_ack_internal),
 .C(clk));

 assign interrupt_ack = interrupt_ack_internal ;

 // Shadow flags

 FDE shadow_carry_flop ( 
 .D(carry_flag),
 .Q(shadow_carry),
 .CE(active_interrupt),
 .C(clk));

 FDE shadow_zero_flop ( 
 .D(zero_flag),
 .Q(shadow_zero),
 .CE(active_interrupt),
 .C(clk));

 // Decode instructions that set or reset interrupt enable

 // synthesis translate_off 
 defparam int_update_lut.INIT = 16'hEAAA ;
 // synthesis translate_on 
 LUT4 int_update_lut( 
 .I0(active_interrupt),
 .I1(instruction[15]),
 .I2(instruction[16]),
 .I3(instruction[17]),
 .O(int_update_enable) )/* synthesis xc_props = "INIT=EAAA"*/;

 // synthesis translate_off 
 defparam int_value_lut.INIT = 8'h04 ;
 // synthesis translate_on 
 LUT3 int_value_lut ( 
 .I0(active_interrupt),
 .I1(instruction[0]),
 .I2(interrupt_ack_internal),
 .O(int_enable_value ))/* synthesis xc_props = "INIT=04"*/;

 FDRE int_enable_flop ( 
 .D(int_enable_value),
 .Q(int_enable),
 .CE(int_update_enable),
 .R(internal_reset),
 .C(clk));
//
////////////////////////////////////////////////////////////////////////////////////
//
// Decodes for the control of the program counter and CALL/RETURN stack
//
////////////////////////////////////////////////////////////////////////////////////
//
 // synthesis translate_off 
 defparam move_group_lut.INIT = 16'h7400 ;
 // synthesis translate_on 
 LUT4 move_group_lut ( 
 .I0(instruction[14]),
 .I1(instruction[15]),
 .I2(instruction[16]),
 .I3(instruction[17]),
 .O(move_group))/* synthesis xc_props = "INIT=7400"*/;

 // synthesis translate_off 
 defparam condition_met_lut.INIT = 16'h5A3C ;
 // synthesis translate_on 
 LUT4 condition_met_lut ( 
 .I0(carry_flag),
 .I1(zero_flag),
 .I2(instruction[10]),
 .I3(instruction[11]),
 .O(condition_met))/* synthesis xc_props = "INIT=5A3C"*/;

 // synthesis translate_off 
 defparam normal_count_lut.INIT = 8'h2F ;
 // synthesis translate_on 
 LUT3 normal_count_lut ( 
 .I0(instruction[12]),
 .I1(condition_met),
 .I2(move_group),
 .O(normal_count ))/* synthesis xc_props = "INIT=2F"*/;

 // synthesis translate_off 
 defparam call_type_lut.INIT = 16'h1000;
 // synthesis translate_on 
 LUT4 call_type_lut ( 
 .I0(instruction[14]),
 .I1(instruction[15]),
 .I2(instruction[16]),
 .I3(instruction[17]),
 .O(call_type ))/* synthesis xc_props = "INIT=1000"*/;

 // synthesis translate_off 
 defparam push_pop_lut.INIT = 16'h5400;
 // synthesis translate_on 
 LUT4 push_pop_lut ( 
 .I0(instruction[14]),
 .I1(instruction[15]),
 .I2(instruction[16]),
 .I3(instruction[17]),
 .O(push_or_pop_type))/* synthesis xc_props = "INIT=5400"*/;

 // synthesis translate_off 
 defparam valid_move_lut.INIT = 4'hD;
 // synthesis translate_on 
 LUT2 valid_move_lut ( 
 .I0(instruction[12]),
 .I1(condition_met),
 .O(valid_to_move ))/* synthesis xc_props = "INIT=D"*/;
//
////////////////////////////////////////////////////////////////////////////////////
//
// The ZERO and CARRY Flags
//
////////////////////////////////////////////////////////////////////////////////////
//
 // Enable for flags

 // synthesis translate_off 
 defparam flag_type_lut.INIT = 16'h41FC;
 // synthesis translate_on 
 LUT4 flag_type_lut ( 
 .I0(instruction[14]),
 .I1(instruction[15]),
 .I2(instruction[16]),
 .I3(instruction[17]),
 .O(flag_type ))/* synthesis xc_props = "INIT=41FC"*/;

 FD flag_write_flop ( 
 .D(flag_type),
 .Q(flag_write),
 .C(clk));

 // synthesis translate_off 
 defparam flag_enable_lut.INIT = 4'h8;
 // synthesis translate_on 
 LUT2 flag_enable_lut ( 
 .I0(t_state),
 .I1(flag_write),
 .O(flag_enable))/* synthesis xc_props = "INIT=8"*/;

 // Zero Flag

 // synthesis translate_off 
 defparam low_zero_lut.INIT = 16'h0001;
 // synthesis translate_on 
 LUT4 low_zero_lut ( 
 .I0(alu_result[0]),
 .I1(alu_result[1]),
 .I2(alu_result[2]),
 .I3(alu_result[3]),
 .O(low_zero ))/* synthesis xc_props = "INIT=0001"*/;

 // synthesis translate_off 
 defparam high_zero_lut.INIT = 16'h0001;
 // synthesis translate_on 
 LUT4 high_zero_lut ( 
 .I0(alu_result[4]),
 .I1(alu_result[5]),
 .I2(alu_result[6]),
 .I3(alu_result[7]),
 .O(high_zero ))/* synthesis xc_props = "INIT=0001"*/;

 MUXCY low_zero_muxcy ( 
 .DI(1'b0),
 .CI(1'b1),
 .S(low_zero),
 .O(low_zero_carry));

 MUXCY high_zero_cymux ( 
 .DI(1'b0),
 .CI(low_zero_carry),
 .S(high_zero),
 .O(high_zero_carry));

 // synthesis translate_off 
 defparam sel_shadow_zero_lut.INIT = 8'h3F;
 // synthesis translate_on 
 LUT3 sel_shadow_zero_lut ( 
 .I0(shadow_zero),
 .I1(instruction[16]),
 .I2(instruction[17]),
 .O(sel_shadow_zero ))/* synthesis xc_props = "INIT=3F"*/;

 MUXCY zero_cymux ( 
 .DI(shadow_zero),
 .CI(high_zero_carry),
 .S(sel_shadow_zero),
 .O(zero_carry ));

 XORCY zero_xor( 
 .LI(1'b0),
 .CI(zero_carry),
 .O(zero_fast_route));
             
 FDRE zero_flag_flop ( 
 .D(zero_fast_route),
 .Q(zero_flag),
 .CE(flag_enable),
 .R(internal_reset),
 .C(clk));

 // Parity detection

 // synthesis translate_off 
 defparam low_parity_lut.INIT = 16'h6996;
 // synthesis translate_on 
 LUT4 low_parity_lut ( 
 .I0(logical_result[0]),
 .I1(logical_result[1]),
 .I2(logical_result[2]),
 .I3(logical_result[3]),
 .O(low_parity ))/* synthesis xc_props = "INIT=6996"*/;

 // synthesis translate_off 
 defparam high_parity_lut.INIT = 16'h6996;
 // synthesis translate_on 
 LUT4 high_parity_lut ( 
 .I0(logical_result[4]),
 .I1(logical_result[5]),
 .I2(logical_result[6]),
 .I3(logical_result[7]),
 .O(high_parity ))/* synthesis xc_props = "INIT=6996"*/;

 MUXCY parity_muxcy ( 
 .DI(1'b0),
 .CI(1'b1),
 .S(low_parity),
 .O(parity_carry) );

 XORCY parity_xor ( 
 .LI(high_parity),
 .CI(parity_carry),
 .O(parity));

 // CARRY flag selection

 // synthesis translate_off 
 defparam sel_parity_lut.INIT = 16'hF3FF;
 // synthesis translate_on 
 LUT4 sel_parity_lut ( 
 .I0(parity),
 .I1(instruction[13]),
 .I2(instruction[15]),
 .I3(instruction[16]),
 .O(sel_parity ))/* synthesis xc_props = "INIT=F3FF"*/;

 // synthesis translate_off 
 defparam sel_arith_carry_lut.INIT = 8'hF3;
 // synthesis translate_on 
 LUT3 sel_arith_carry_lut ( 
 .I0(arith_carry),
 .I1(instruction[16]),
 .I2(instruction[17]),
 .O(sel_arith_carry ))/* synthesis xc_props = "INIT=F3"*/;

 // synthesis translate_off 
 defparam sel_shift_carry_lut.INIT = 4'hC;
 // synthesis translate_on 
 LUT2 sel_shift_carry_lut ( 
 .I0(shift_carry),
 .I1(instruction[15]),
 .O(sel_shift_carry ))/* synthesis xc_props = "INIT=C"*/;

 // synthesis translate_off 
 defparam sel_shadow_carry_lut.INIT = 4'h3;
 // synthesis translate_on 
 LUT2 sel_shadow_carry_lut ( 
 .I0(shadow_carry),
 .I1(instruction[17]),
 .O(sel_shadow_carry ))/* synthesis xc_props = "INIT=3"*/;

 MUXCY sel_shadow_muxcy ( 
 .DI(shadow_carry),
 .CI(1'b0),
 .S(sel_shadow_carry),
 .O(sel_carry[0]) );

 MUXCY sel_shift_muxcy ( 
 .DI(shift_carry),
 .CI(sel_carry[0]),
 .S(sel_shift_carry),
 .O(sel_carry[1]) );

 MUXCY sel_arith_muxcy ( 
 .DI(arith_carry),
 .CI(sel_carry[1]),
 .S(sel_arith_carry),
 .O(sel_carry[2]) );

 MUXCY sel_parity_muxcy ( 
 .DI(parity),
 .CI(sel_carry[2]),
 .S(sel_parity),
 .O(sel_carry[3]) );

 XORCY carry_xor(
 .LI(1'b0),
 .CI(sel_carry[3]),
 .O(carry_fast_route));
             
 FDRE carry_flag_flop ( 
 .D(carry_fast_route),
 .Q(carry_flag),
 .CE(flag_enable),
 .R(internal_reset),
 .C(clk));
//
////////////////////////////////////////////////////////////////////////////////////
//
// The Program Counter
//
// Definition of a 10-bit counter which can be loaded from two sources
//
////////////////////////////////////////////////////////////////////////////////////
//  

 INV invert_enable(// Inverter should be implemented in the CE to flip flops
 .I(t_state),
 .O(pc_enable)); 
 
 // pc_loop

 // synthesis translate_off 
 defparam vector_select_mux_0.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 vector_select_mux_0 ( 
 .I0(instruction[15]),
 .I1(instruction[0]),
 .I2(stack_pop_data[0]), 
 .O(pc_vector[0]))/* synthesis xc_props = "INIT=E4"*/;

 // synthesis translate_off 
 defparam value_select_mux_0.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 value_select_mux_0(
 .I0(normal_count),
 .I1(inc_pc_vector[0]),
 .I2(pc[0]),
 .O(pc_value[0]))/* synthesis xc_props = "INIT=E4"*/;

 FDRSE pc_loop_register_bit_0 ( 
 .D(inc_pc_value[0]),
 .Q(pc[0]),
 .R(internal_reset),
 .S(active_interrupt),
 .CE(pc_enable),
 .C(clk));

 MUXCY pc_vector_muxcy_0 ( 
 .DI(1'b0),
 .CI(instruction[13]),
 .S(pc_vector[0]),
 .O(pc_vector_carry[0]));

 XORCY pc_vector_xor_0 ( 
 .LI(pc_vector[0]),
 .CI(instruction[13]),
 .O(inc_pc_vector[0]));

 MUXCY pc_value_muxcy_0 ( 
 .DI(1'b0),
 .CI(normal_count),
 .S(pc_value[0]),
 .O(pc_value_carry[0]));

 XORCY pc_value_xor_0 ( 
 .LI(pc_value[0]),
 .CI(normal_count),
 .O(inc_pc_value[0]));

 // synthesis translate_off 
 defparam vector_select_mux_1.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 vector_select_mux_1 ( 
 .I0(instruction[15]),
 .I1(instruction[1]),
 .I2(stack_pop_data[1]), 
 .O(pc_vector[1]))/* synthesis xc_props = "INIT=E4"*/;

 // synthesis translate_off 
 defparam value_select_mux_1.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 value_select_mux_1(
 .I0(normal_count),
 .I1(inc_pc_vector[1]),
 .I2(pc[1]),
 .O(pc_value[1]))/* synthesis xc_props = "INIT=E4"*/;

 FDRSE pc_loop_register_bit_1 ( 
 .D(inc_pc_value[1]),
 .Q(pc[1]),
 .R(internal_reset),
 .S(active_interrupt),
 .CE(pc_enable),
 .C(clk));

 MUXCY pc_vector_muxcy_1 ( 
 .DI(1'b0),
 .CI(pc_vector_carry[0]),
 .S(pc_vector[1]),
 .O(pc_vector_carry[1]));

 XORCY pc_vector_xor_1 ( 
 .LI(pc_vector[1]),
 .CI(pc_vector_carry[0]),
 .O(inc_pc_vector[1]));

 MUXCY pc_value_muxcy_1 ( 
 .DI(1'b0),
 .CI(pc_value_carry[0]),
 .S(pc_value[1]),
 .O(pc_value_carry[1]));

 XORCY pc_value_xor_1 ( 
 .LI(pc_value[1]),
 .CI(pc_value_carry[0]),
 .O(inc_pc_value[1]));
 
 // synthesis translate_off 
 defparam vector_select_mux_2.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 vector_select_mux_2 ( 
 .I0(instruction[15]),
 .I1(instruction[2]),
 .I2(stack_pop_data[2]), 
 .O(pc_vector[2]))/* synthesis xc_props = "INIT=E4"*/;

 // synthesis translate_off 
 defparam value_select_mux_2.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 value_select_mux_2(
 .I0(normal_count),
 .I1(inc_pc_vector[2]),
 .I2(pc[2]),
 .O(pc_value[2]))/* synthesis xc_props = "INIT=E4"*/;

 FDRSE pc_loop_register_bit_2 ( 
 .D(inc_pc_value[2]),
 .Q(pc[2]),
 .R(internal_reset),
 .S(active_interrupt),
 .CE(pc_enable),
 .C(clk));

 MUXCY pc_vector_muxcy_2 ( 
 .DI(1'b0),
 .CI(pc_vector_carry[1]),
 .S(pc_vector[2]),
 .O(pc_vector_carry[2]));

 XORCY pc_vector_xor_2 ( 
 .LI(pc_vector[2]),
 .CI(pc_vector_carry[1]),
 .O(inc_pc_vector[2]));

 MUXCY pc_value_muxcy_2 ( 
 .DI(1'b0),
 .CI(pc_value_carry[1]),
 .S(pc_value[2]),
 .O(pc_value_carry[2]));

 XORCY pc_value_xor_2 ( 
 .LI(pc_value[2]),
 .CI(pc_value_carry[1]),
 .O(inc_pc_value[2]));
 
 // synthesis translate_off 
 defparam vector_select_mux_3.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 vector_select_mux_3 ( 
 .I0(instruction[15]),
 .I1(instruction[3]),
 .I2(stack_pop_data[3]), 
 .O(pc_vector[3]))/* synthesis xc_props = "INIT=E4"*/;

 // synthesis translate_off 
 defparam value_select_mux_3.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 value_select_mux_3(
 .I0(normal_count),
 .I1(inc_pc_vector[3]),
 .I2(pc[3]),
 .O(pc_value[3]))/* synthesis xc_props = "INIT=E4"*/;

 FDRSE pc_loop_register_bit_3 ( 
 .D(inc_pc_value[3]),
 .Q(pc[3]),
 .R(internal_reset),
 .S(active_interrupt),
 .CE(pc_enable),
 .C(clk));

 MUXCY pc_vector_muxcy_3 ( 
 .DI(1'b0),
 .CI(pc_vector_carry[2]),
 .S(pc_vector[3]),
 .O(pc_vector_carry[3]));

 XORCY pc_vector_xor_3 ( 
 .LI(pc_vector[3]),
 .CI(pc_vector_carry[2]),
 .O(inc_pc_vector[3]));

 MUXCY pc_value_muxcy_3 ( 
 .DI(1'b0),
 .CI(pc_value_carry[2]),
 .S(pc_value[3]),
 .O(pc_value_carry[3]));

 XORCY pc_value_xor_3 ( 
 .LI(pc_value[3]),
 .CI(pc_value_carry[2]),
 .O(inc_pc_value[3]));
 
 // synthesis translate_off 
 defparam vector_select_mux_4.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 vector_select_mux_4 ( 
 .I0(instruction[15]),
 .I1(instruction[4]),
 .I2(stack_pop_data[4]), 
 .O(pc_vector[4]))/* synthesis xc_props = "INIT=E4"*/;

 // synthesis translate_off 
 defparam value_select_mux_4.INIT = 8'hE4;
 // synthesis translate_on 
 LUT3 value_select_mux_4(
 .I0(normal_count),
 .I1(inc_pc_vector[4]),
 .I2(pc[4]),
 .O(pc_value[4]))/* synthesis xc_props = "INIT=E4"*/;

 FDRSE pc_loop_register_bit_4 ( 
 .D(inc_pc_value[4]),
 .Q(pc[4]),
 .R(internal_reset),
 .S(active_interrupt),
 .CE(pc_enable),
 .C(clk));

 MUXCY pc_vector_muxcy_4 ( 
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