Prev Page | Hierarchy | Files | Modules | Signals | Tasks | Functions | Help |
A | C | D | E | F | H | I | K | L | M | N | O | P | R | S | T | U | V | W | X | Y | Z |
Z |
Connects down to: | MUXCY:zero_cymux:O , XORCY:zero_xor:CI |
Connects down to: | XORCY:zero_xor:O , FDRE:zero_flag_flop:D |
Connects down to: | LUT4:decode_lut:I1 |
Connects up to: | kcpsm2:test_flags:zero_flag |
Connects down to: | FDE:preserve_zero_flop:D |
Connects up to: | kcpsm2:interrupt_control:zero_flag |
Connects down to: | zero_flag_logic:zero:zero_flag , flag_test:test_flags:zero_flag , interrupt_logic:interrupt_control:zero_flag |
Connects down to: | FDE:shadow_zero_flop:D , LUT4:condition_met_lut:I1 , FDRE:zero_flag_flop:Q |
Connects down to: | FDRE:zero_flag_flop:Q |
Connects up to: | kcpsm2:zero:zero_flag |
A | C | D | E | F | H | I | K | L | M | N | O | P | R | S | T | U | V | W | X | Y | Z |
Hierarchy | Files | Modules | Signals | Tasks | Functions | Help |
This page: | Maintained by: | pablo.N@SPAM.bleyer.org |
Created: | Tue Mar 14 03:42:56 2006 |
Verilog converted to html by v2html 7.30 (written by Costas Calamvokis). | Help |